From d639c61f8338dcc221f88f350e2804e12e2dfaaf Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Mon, 5 Oct 2009 15:18:43 +0200 Subject: [PATCH 29/69] gta02: Add battery driver --- arch/arm/mach-s3c2440/Makefile | 1 + arch/arm/mach-s3c2440/gta02-fiq.c | 5 + arch/arm/mach-s3c2440/gta02-hdq.c | 414 ++++++++++++++++++++++++ arch/arm/mach-s3c2440/include/mach/gta02-hdq.h | 23 ++ arch/arm/mach-s3c2440/mach-gta02.c | 86 +++++ 5 files changed, 529 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-s3c2440/gta02-hdq.c create mode 100644 arch/arm/mach-s3c2440/include/mach/gta02-hdq.h diff --git a/arch/arm/mach-s3c2440/Makefile b/arch/arm/mach-s3c2440/Makefile index 0701323..035d116 100644 --- a/arch/arm/mach-s3c2440/Makefile +++ b/arch/arm/mach-s3c2440/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_MACH_NEO1973_GTA02) += mach-gta02.o \ gta02-pm-gsm.o \ gta02-pm-wlan.o \ gta02-fiq.o \ + gta02-hdq.o \ # extra machine support diff --git a/arch/arm/mach-s3c2440/gta02-fiq.c b/arch/arm/mach-s3c2440/gta02-fiq.c index 9f7a0f8..6a9061d 100644 --- a/arch/arm/mach-s3c2440/gta02-fiq.c +++ b/arch/arm/mach-s3c2440/gta02-fiq.c @@ -7,6 +7,7 @@ #include #include #include +#include /* * GTA02 FIQ related @@ -17,6 +18,9 @@ #define DIVISOR_FROM_US(x) ((x) << 3) +#define FIQ_DIVISOR_HDQ DIVISOR_FROM_US(HDQ_SAMPLE_PERIOD_US) +extern int hdq_fiq_handler(void); + /* Global data related to our fiq source */ static uint32_t gta02_fiq_ack_mask; static const int gta02_gta02_fiq_timer_id = 2; @@ -35,6 +39,7 @@ void gta02_fiq_handler(void) * thankfully and taken care of by the fiq-basis patch */ + keep_running = hdq_fiq_handler(); if (!keep_running) { /* Disable irq */ intmask = __raw_readl(S3C2410_INTMSK); diff --git a/arch/arm/mach-s3c2440/gta02-hdq.c b/arch/arm/mach-s3c2440/gta02-hdq.c new file mode 100644 index 0000000..a1dadc2 --- /dev/null +++ b/arch/arm/mach-s3c2440/gta02-hdq.c @@ -0,0 +1,414 @@ +/* + * HDQ generic GPIO bitbang driver using FIQ + * + * (C) 2006-2007 by Openmoko, Inc. + * Author: Andy Green + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include + +#define HDQ_READ 0 + +enum hdq_bitbang_states { + HDQB_IDLE = 0, + HDQB_TX_BREAK, + HDQB_TX_BREAK_RECOVERY, + HDQB_ADS_CALC, + HDQB_ADS_LOW, + HDQB_ADS_HIGH, + HDQB_WAIT_RX, + HDQB_DATA_RX_LOW, + HDQB_DATA_RX_HIGH, + HDQB_WAIT_TX, +}; + +static struct hdq_priv { + struct mutex lock; /* if you want to use hdq, you have to take lock */ + u8 hdq_probed; /* nonzero after HDQ driver probed */ + u8 hdq_ads; /* b7..b6 = register address, b0 = r/w */ + u8 hdq_tx_data; /* data to tx for write action */ + u8 hdq_rx_data; /* data received in read action */ + u8 hdq_request_ctr; /* incremented by "user" to request a transfer */ + u8 hdq_transaction_ctr; /* incremented after each transfer */ + u8 hdq_error; /* 0 = no error */ + u8 hdq_ctr; + u8 hdq_ctr2; + u8 hdq_bit; + u8 hdq_shifter; + u8 hdq_tx_data_done; + enum hdq_bitbang_states hdq_state; + int reported_error; + + struct hdq_platform_data *pdata; +} hdq_priv; + + +static void hdq_bad(void) +{ + if (!hdq_priv.reported_error) + printk(KERN_ERR "HDQ error: %d\n", hdq_priv.hdq_error); + hdq_priv.reported_error = 1; +} + +static void hdq_good(void) +{ + if (hdq_priv.reported_error) + printk(KERN_INFO "HDQ responds again\n"); + hdq_priv.reported_error = 0; +} + +int hdq_fiq_handler(void) +{ + if (!hdq_priv.hdq_probed) + return 0; + + switch (hdq_priv.hdq_state) { + case HDQB_IDLE: + if (hdq_priv.hdq_request_ctr == hdq_priv.hdq_transaction_ctr) + break; + hdq_priv.hdq_ctr = 250 / HDQ_SAMPLE_PERIOD_US; + hdq_priv.pdata->gpio_set(0); + hdq_priv.pdata->gpio_dir_out(); + hdq_priv.hdq_tx_data_done = 0; + hdq_priv.hdq_state = HDQB_TX_BREAK; + break; + + case HDQB_TX_BREAK: /* issue low for > 190us */ + if (--hdq_priv.hdq_ctr == 0) { + hdq_priv.hdq_ctr = 60 / HDQ_SAMPLE_PERIOD_US; + hdq_priv.hdq_state = HDQB_TX_BREAK_RECOVERY; + hdq_priv.pdata->gpio_set(1); + } + break; + + case HDQB_TX_BREAK_RECOVERY: /* issue low for > 40us */ + if (--hdq_priv.hdq_ctr) + break; + hdq_priv.hdq_shifter = hdq_priv.hdq_ads; + hdq_priv.hdq_bit = 8; /* 8 bits of ads / rw */ + hdq_priv.hdq_tx_data_done = 0; /* doing ads */ + /* fallthru on last one */ + case HDQB_ADS_CALC: + if (hdq_priv.hdq_shifter & 1) + hdq_priv.hdq_ctr = 50 / HDQ_SAMPLE_PERIOD_US; + else + hdq_priv.hdq_ctr = 120 / HDQ_SAMPLE_PERIOD_US; + /* carefully precompute the other phase length */ + hdq_priv.hdq_ctr2 = (210 - (hdq_priv.hdq_ctr * + HDQ_SAMPLE_PERIOD_US)) / HDQ_SAMPLE_PERIOD_US; + hdq_priv.hdq_state = HDQB_ADS_LOW; + hdq_priv.hdq_shifter >>= 1; + hdq_priv.hdq_bit--; + hdq_priv.pdata->gpio_set(0); + break; + + case HDQB_ADS_LOW: + if (--hdq_priv.hdq_ctr) + break; + hdq_priv.pdata->gpio_set(1); + hdq_priv.hdq_state = HDQB_ADS_HIGH; + break; + + case HDQB_ADS_HIGH: + if (--hdq_priv.hdq_ctr2 > 1) /* account for HDQB_ADS_CALC */ + break; + if (hdq_priv.hdq_bit) { /* more bits to do */ + hdq_priv.hdq_state = HDQB_ADS_CALC; + break; + } + /* no more bits, wait until hdq_priv.hdq_ctr2 exhausted */ + if (hdq_priv.hdq_ctr2) + break; + /* ok no more bits and very last state */ + hdq_priv.hdq_ctr = 60 / HDQ_SAMPLE_PERIOD_US; + /* FIXME 0 = read */ + if (hdq_priv.hdq_ads & 0x80) { /* write the byte out */ + /* set delay before payload */ + hdq_priv.hdq_ctr = 300 / HDQ_SAMPLE_PERIOD_US; + /* already high, no need to write */ + hdq_priv.hdq_state = HDQB_WAIT_TX; + break; + } + /* read the next byte */ + hdq_priv.hdq_bit = 8; /* 8 bits of data */ + hdq_priv.hdq_ctr = 2500 / HDQ_SAMPLE_PERIOD_US; + hdq_priv.hdq_state = HDQB_WAIT_RX; + hdq_priv.pdata->gpio_dir_in(); + break; + + case HDQB_WAIT_TX: /* issue low for > 40us */ + if (--hdq_priv.hdq_ctr) + break; + if (!hdq_priv.hdq_tx_data_done) { /* was that the data sent? */ + hdq_priv.hdq_tx_data_done++; + hdq_priv.hdq_shifter = hdq_priv.hdq_tx_data; + hdq_priv.hdq_bit = 8; /* 8 bits of data */ + hdq_priv.hdq_state = HDQB_ADS_CALC; /* start sending */ + break; + } + hdq_priv.hdq_error = 0; + hdq_priv.hdq_transaction_ctr = hdq_priv.hdq_request_ctr; + hdq_priv.hdq_state = HDQB_IDLE; /* all tx is done */ + /* idle in input mode, it's pulled up by 10K */ + hdq_priv.pdata->gpio_dir_in(); + break; + + case HDQB_WAIT_RX: /* wait for battery to talk to us */ + if (hdq_priv.pdata->gpio_get() == 0) { + /* it talks to us! */ + hdq_priv.hdq_ctr2 = 1; + hdq_priv.hdq_bit = 8; /* 8 bits of data */ + /* timeout */ + hdq_priv.hdq_ctr = 500 / HDQ_SAMPLE_PERIOD_US; + hdq_priv.hdq_state = HDQB_DATA_RX_LOW; + break; + } + if (--hdq_priv.hdq_ctr == 0) { /* timed out, error */ + hdq_priv.hdq_error = 1; + hdq_priv.hdq_transaction_ctr = hdq_priv.hdq_request_ctr; + hdq_priv.hdq_state = HDQB_IDLE; /* abort */ + } + break; + + /* + * HDQ basically works by measuring the low time of the bit cell + * 32-50us --> '1', 80 - 145us --> '0' + */ + + case HDQB_DATA_RX_LOW: + if (hdq_priv.pdata->gpio_get()) { + hdq_priv.hdq_rx_data >>= 1; + if (hdq_priv.hdq_ctr2 <= (65 / HDQ_SAMPLE_PERIOD_US)) + hdq_priv.hdq_rx_data |= 0x80; + + if (--hdq_priv.hdq_bit == 0) { + hdq_priv.hdq_error = 0; + hdq_priv.hdq_transaction_ctr = + hdq_priv.hdq_request_ctr; + + hdq_priv.hdq_state = HDQB_IDLE; + } else + hdq_priv.hdq_state = HDQB_DATA_RX_HIGH; + /* timeout */ + hdq_priv.hdq_ctr = 1000 / HDQ_SAMPLE_PERIOD_US; + hdq_priv.hdq_ctr2 = 1; + break; + } + hdq_priv.hdq_ctr2++; + if (--hdq_priv.hdq_ctr) + break; + /* timed out, error */ + hdq_priv.hdq_error = 2; + hdq_priv.hdq_transaction_ctr = hdq_priv.hdq_request_ctr; + hdq_priv.hdq_state = HDQB_IDLE; /* abort */ + break; + + case HDQB_DATA_RX_HIGH: + if (!hdq_priv.pdata->gpio_get()) { + /* it talks to us! */ + hdq_priv.hdq_ctr2 = 1; + /* timeout */ + hdq_priv.hdq_ctr = 400 / HDQ_SAMPLE_PERIOD_US; + hdq_priv.hdq_state = HDQB_DATA_RX_LOW; + break; + } + if (--hdq_priv.hdq_ctr) + break; + /* timed out, error */ + hdq_priv.hdq_error = 3; + hdq_priv.hdq_transaction_ctr = hdq_priv.hdq_request_ctr; + + /* we're in input mode already */ + hdq_priv.hdq_state = HDQB_IDLE; /* abort */ + break; + } + + /* Are we interested in keeping the FIQ source alive ? */ + if (hdq_priv.hdq_state != HDQB_IDLE) + return 1; + else + return 0; +} + +static int fiq_busy(void) +{ + int request; + int transact; + + request = (volatile u8)hdq_priv.hdq_request_ctr; + transact = (volatile u8)hdq_priv.hdq_transaction_ctr; + return (request != transact); +} + +int hdq_read(struct device *dev, unsigned int address) +{ + int count_sleeps = 5; + int ret = -ETIME; + + if (!hdq_priv.hdq_probed) + return -EINVAL; + + mutex_lock(&hdq_priv.lock); + + hdq_priv.hdq_error = 0; + hdq_priv.hdq_ads = address | HDQ_READ; + hdq_priv.hdq_request_ctr++; + hdq_priv.pdata->kick_fiq(); + /* + * FIQ takes care of it while we block our calling process + * But we're not spinning -- other processes run normally while + * we wait for the result + */ + while (count_sleeps--) { + msleep(10); /* valid transaction always completes in < 10ms */ + + if (fiq_busy()) + continue; + + if (hdq_priv.hdq_error) { + hdq_bad(); + goto done; /* didn't see a response in good time */ + } + hdq_good(); + + ret = hdq_priv.hdq_rx_data; + goto done; + } + +done: + mutex_unlock(&hdq_priv.lock); + return ret; +} +EXPORT_SYMBOL_GPL(hdq_read); + +/* sysfs */ + +static ssize_t hdq_sysfs_dump(struct device *dev, struct device_attribute *attr, + char *buf) +{ + int n; + int v; + u8 u8a[128]; /* whole address space for HDQ */ + char *end = buf; + + if (!hdq_priv.hdq_probed) + return -EINVAL; + + /* the dump does not take care about 16 bit regs, because at this + * bus level we don't know about the chip details + */ + for (n = 0; n < sizeof(u8a); n++) { + v = hdq_read(NULL, n); + if (v < 0) + goto bail; + u8a[n] = v; + } + + for (n = 0; n < sizeof(u8a); n += 16) { + hex_dump_to_buffer(u8a + n, sizeof(u8a), 16, 1, end, 4096, 0); + end += strlen(end); + *end++ = '\n'; + *end = '\0'; + } + return end - buf; + +bail: + return sprintf(buf, "ERROR %d\n", v); +} + + +static DEVICE_ATTR(dump, 0400, hdq_sysfs_dump, NULL); + +#ifdef CONFIG_PM +static int hdq_suspend(struct platform_device *pdev, pm_message_t state) +{ + /* after 18s of this, the battery monitor will also go to sleep */ + hdq_priv.pdata->gpio_dir_in(); + hdq_priv.pdata->disable_fiq(); + return 0; +} + +static int hdq_resume(struct platform_device *pdev) +{ + hdq_priv.pdata->gpio_set(1); + hdq_priv.pdata->gpio_dir_out(); + hdq_priv.pdata->enable_fiq(); + return 0; +} +#endif + +static int __devinit hdq_probe(struct platform_device *pdev) +{ + struct hdq_platform_data *pdata = pdev->dev.platform_data; + int ret; + + if (!pdata) + return -ENXIO; + + mutex_init(&hdq_priv.lock); + + /* set our HDQ comms pin from the platform data */ + hdq_priv.pdata = pdata; + + hdq_priv.pdata->gpio_set(1); + hdq_priv.pdata->gpio_dir_out(); + + /* Initialize FIQ */ + if (hdq_priv.pdata->enable_fiq() < 0) { + dev_err(&pdev->dev, "Could not enable FIQ source\n"); + return -EINVAL; + } + + ret = device_create_file(&pdev->dev, &dev_attr_dump); + if (ret) + return ret; + + hdq_priv.hdq_probed = 1; /* we are ready to do stuff now */ + + hdq_priv.pdata = pdata; + + return 0; +} + +static int __devexit hdq_remove(struct platform_device *pdev) +{ + device_remove_file(&pdev->dev, &dev_attr_dump); + return 0; +} + +static struct platform_driver hdq_driver = { + .probe = hdq_probe, + .remove = hdq_remove, +#ifdef CONFIG_PM + .suspend = hdq_suspend, + .resume = hdq_resume, +#endif + .driver = { + .name = "hdq", + }, +}; + +static int __init hdq_init(void) +{ + return platform_driver_register(&hdq_driver); +} +module_init(hdq_init); + +static void __exit hdq_exit(void) +{ + platform_driver_unregister(&hdq_driver); +} +module_exit(hdq_exit); + +MODULE_AUTHOR("Andy Green "); +MODULE_DESCRIPTION("HDQ driver"); diff --git a/arch/arm/mach-s3c2440/include/mach/gta02-hdq.h b/arch/arm/mach-s3c2440/include/mach/gta02-hdq.h new file mode 100644 index 0000000..ba98f8f --- /dev/null +++ b/arch/arm/mach-s3c2440/include/mach/gta02-hdq.h @@ -0,0 +1,23 @@ +#ifndef __LINUX_HDQ_H__ +#define __LINUX_HDQ_H__ + +#include + +#define HDQ_SAMPLE_PERIOD_US 10 + +/* platform data */ + +struct hdq_platform_data { + void (*gpio_dir_out)(void); + void (*gpio_dir_in)(void); + void (*gpio_set)(int); + int (*gpio_get)(void); + + int (*enable_fiq)(void); + void (*disable_fiq)(void); + void (*kick_fiq)(void); +}; + +int hdq_read(struct device *dev, unsigned int address); + +#endif diff --git a/arch/arm/mach-s3c2440/mach-gta02.c b/arch/arm/mach-s3c2440/mach-gta02.c index d599a8c..cf1b8ee 100644 --- a/arch/arm/mach-s3c2440/mach-gta02.c +++ b/arch/arm/mach-s3c2440/mach-gta02.c @@ -102,6 +102,9 @@ #include +#include +#include + #include #include #include @@ -350,6 +353,20 @@ static struct platform_device gta02_glamo_dev = { #define ADC_NOM_CHG_DETECT_1A 6 #define ADC_NOM_CHG_DETECT_USB 43 +static int gta02_get_charger_online_status(void) +{ + struct pcf50633 *pcf = gta02_pcf; + + return pcf50633_mbc_get_status(pcf) & PCF50633_MBC_USB_ONLINE; +} + +static int gta02_get_charger_active_status(void) +{ + struct pcf50633 *pcf = gta02_pcf; + + return pcf50633_mbc_get_status(pcf) & PCF50633_MBC_USB_ACTIVE; +} + static void gta02_configure_pmu_for_charger(struct pcf50633 *pcf, void *unused, int res) { @@ -418,6 +435,8 @@ static void gta02_udc_vbus_draw(unsigned int ma) #else /* !CONFIG_CHARGER_PCF50633 */ #define gta02_pmu_event_callback NULL #define gta02_udc_vbus_draw NULL +#define gta02_get_charger_online_status NULL +#define gta02_get_charger_active_status NULL #endif /* @@ -825,6 +844,62 @@ static struct platform_device gta02_pwm_leds_device = { } }; +/* BQ27000 Battery */ + +static struct bq27000_platform_data bq27000_pdata = { + .read = hdq_read, + .name = "battery", +}; + +static struct platform_device bq27000_battery_device = { + .name = "bq27000-battery", + .dev = { + .platform_data = &bq27000_pdata, + }, +}; + +/* HDQ */ + +static void gta02_hdq_gpio_direction_out(void) +{ + s3c2410_gpio_cfgpin(GTA02v5_GPIO_HDQ, S3C2410_GPIO_OUTPUT); +} + +static void gta02_hdq_gpio_direction_in(void) +{ + s3c2410_gpio_cfgpin(GTA02v5_GPIO_HDQ, S3C2410_GPIO_INPUT); +} + +static void gta02_hdq_gpio_set_value(int val) +{ + s3c2410_gpio_setpin(GTA02v5_GPIO_HDQ, val); +} + +static int gta02_hdq_gpio_get_value(void) +{ + return s3c2410_gpio_getpin(GTA02v5_GPIO_HDQ); +} + +struct hdq_platform_data gta02_hdq_platform_data = { + .gpio_dir_out = gta02_hdq_gpio_direction_out, + .gpio_dir_in = gta02_hdq_gpio_direction_in, + .gpio_set = gta02_hdq_gpio_set_value, + .gpio_get = gta02_hdq_gpio_get_value, + + .enable_fiq = gta02_fiq_enable, + .disable_fiq = gta02_fiq_disable, + .kick_fiq = gta02_fiq_kick, +}; + +struct platform_device gta02_hdq_device = { + .name = "hdq", + .id = -1, + .dev = { + .platform_data = >a02_hdq_platform_data, + .parent = &s3c_device_timer[2].dev, + }, +}; + static void __init gta02_map_io(void) { s3c24xx_init_io(gta02_iodesc, ARRAY_SIZE(gta02_iodesc)); @@ -864,6 +939,7 @@ static struct platform_device *gta02_devices[] __initdata = { /* These guys DO need to be children of PMU. */ static struct platform_device *gta02_devices_pmu_children[] = { + >a02_hdq_device, }; @@ -915,6 +991,11 @@ static struct platform_device *gta02_gsm_supply_children[] = { >a02_pm_gsm_dev, }; +static struct platform_device *gta02_hdq_children[] = { + &bq27000_battery_device, +}; + + static struct gta02_device_children gta02_device_children[] = { { .dev_name = "glamo-gpio.0", @@ -935,6 +1016,11 @@ static struct gta02_device_children gta02_device_children[] = { .dev_name = "spi2.0", .probed_callback = gta02_jbt6k74_probe_completed, }, + { + .dev_name = "hdq", + .num_children = 1, + .children = gta02_hdq_children, + }, }; static int gta02_add_child_devices(struct device *parent, -- 1.7.2.5